There is known a technology in which a stress liner film having a tensile stress or a compressive stress is formed on an upper surface of a FET (Field Effect Transistor) for use in a logic circuit and in which a strain is applied to the FET, thereby enhancing the mobility of carriers and increasing an operation speed. Plasma CVD (Chemical Vapor Deposition) or the like is used in forming the stress liner film. Silicon nitride or the like is used as the material of the stress liner film. The plasma CVD has an advantage in that the stress acting direction (the tension direction or the compression direction) and the magnitude of a stress can be controlled by changing plasma conditions.
In recent years, the development of a transistor having a three-dimensional structure, which is capable of additionally increasing the degree of integration and reducing the power consumption, is underway. Since the device of this kind has a protrusion portion with a large level difference, there is difficulty involved in forming a stress liner film through the use of a CVD method which provides coating performance with a low level difference.
Further, a film formation method, which provides coating performance with a higher level difference than the CVD method, such as an ALD (Atomic Layer Deposition) method and an MLD (Molecular Layer Deposition) method (both of which will be hereinafter referred to as an ALD method) is also used. The ALD method is a film formation method in which atomic layers or molecular layers are deposited by repeating a step of sequentially supplying different kinds of process gases including a raw material into a reaction vessel and causing reaction of these process gases while allowing the raw material to be adsorbed to the surface of a substrate. As a film material with which a stress liner film can be formed through the use of the ALD method, it is possible to cite the aforementioned silicon nitride. However, it is known that the ALD method has a difficulty in giving a large enough stress.
As one example of a double patterning technology for miniaturizing a wiring pattern, there is available a method of forming deposition portions called sidewalls on the opposite lateral walls of a linear mask pattern, removing the mask pattern, and patterning a lower layer film using the remaining sidewalls as new masks. A film formation process such as a CVD method or an ALD method is used in forming the sidewalls. Stresses generated during the film formation remain within the sidewalls. For that reason, if the aspect ratio of the sidewalls becomes higher along with the miniaturization of the wiring pattern, there is posed a problem in that pattern collapse may occur due to the increased influence of stresses acting on the sidewalls.
In this regard, there has been suggested a technology in which, when forming a deposition layer of metal oxide or metal oxynitride by an ALD method, ultraviolet rays are irradiated on a substrate supplied with a precursor gas, thereby dissociating impurities existing in a molecular layer formed on a substrate surface and terminating the surface of the molecular layer with OH groups having increased reaction activity. However, there is still a need of a method of controlling stresses generated in a deposition layer and a film material to which the method can be applied.